Design of Low Power Viterbi Decoder Using Asynchronous Techniques

In today’s digital communication systems, Convolutional codes are broadly used in channel coding techniques. The Viterbi decoder due to its high performance is commonly used for decoding the convolution codes. Fast developments in the communication field have created a rising demand for high speed and low power Viterbi decoders with long battery life, low power dissipation and low weight. Despite the significant progress in the last decade, the problem of power dissipation in the Viterbi decoders still remains challenging and requires further technical solutions. The proposed method is focused on the design of VLSI architecture for a Viterbi Decoder using low power VLSI design techniques at circuit level with asynchronous QDI templates and Differential Cascode Voltage Switch Logic (DCVSL). The design of various units of Viterbi Decoder is done using T – SPICE in 0.25um Technology. The simulation results of the asynchronous design shows 56.20% power reduction with a supply voltage of 2.5 Vdd is achieved when compared to synchronous design.